Status Register
| FIFO_RX_WATERMARK | FIFO reached Receive watermark level; not qualified with data transfer. |
| FIFO_TX_WATERMARK | FIFO reached Transmit watermark level; not qualified with data transfer. |
| FIFO_EMPTY | FIFO is empty status |
| FIFO_FULL | FIFO is full status |
| CMDFSMSTATES | Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The command FSM state is represented using 19 bits. The STATUS Register(7:4) has 4 bits to represent the command FSM states. Using these 4 bits, only 16 states can be represented. Thus three states cannot be represented in the STATUS(7:4) register. The three states that are not represented in the STATUS Register(7:4) are: - Bit 16 - Wait for CCS - Bit 17 - Send CCSD - Bit 18 - Boot Mode Due to this, while command FSM is in Wait for CCS state or Send CCSD or Boot Mode, the Status register indicates status as 0 for the bit field 7:4. |
| DATA_3_STATUS | Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present |
| DATA_BUSY | Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy |
| DATA_STATE_MC_BUSY | Data transmit or receive state-machine is busy |
| RESPONSE_INDEX | Index of previous response, including any auto-stop sent by core. |
| FIFO_COUNT | FIFO count - Number of filled locations in FIFO |
| DMA_ACK | DMA acknowledge signal state |
| DMA_REQ | DMA request signal state |